The present invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated method for fabricating it, and in particular to a nonvolatile semiconductor memory cell having a memory transistor and a selection transistor connected thereto.
FIG. 1 shows a simplified sectional view of such a conventional nonvolatile two-transistor semiconductor memory cell, in which case, in a semiconductor substrate 1, which is p-doped, for example, a selection transistor AT and a memory transistor ST are formed and are connected to one another via a common source/drain region 2.
The memory transistor ST usually comprises an insulating tunnel oxide layer 3, a conductive floating gate formed on layer 4, an insulating dielectric layer 5 and a conductive control gate layer 6. For storing information, charges are introduced from the semiconductor substrate 1 into the floating gate on layer 4. Examples of methods for introducing the charges into the floating gate layer 4 are injection of hot charge carriers and Fowler-Nordheim tunnelling.
For the selection or driving of the actual memory transistor ST, the two-transistor semiconductor memory cell furthermore has a selection transistor AT which, as field-effect transistor, essentially has a gate oxide layer 3′ and a control gate formed on layer 4 lying above the latter. The floating gate layer of the memory transistor and the control gate layer of the selection transistor are usually composed of the same material, such as e.g. polysilicon, which is n+-doped, for example, and is illustrated in FIG. 1 as layer 4.
In the case of such nonvolatile two-transistor semiconductor memory cells, the charge retention properties, in particular, are of greater importance for the use and the reliability. Said charge retention properties are usually limited by (anomalous) loss of charge resulting from leakage phenomena. Said loss of charge takes place for example on account of traps or imperfections within the tunnel oxide 3, a tunnelling mechanism being assisted by said imperfections or traps (trap assisted tunnelling). In order to avoid such leakage currents or in order to improve the charge retention properties, the layer thicknesses for the tunnel oxide layer 3 and/or the dielectric layer 5 are usually increased, as a result of which, however, the electrical properties of the memory cell deteriorate and it is necessary to raise in particular the operating voltages for reading from, writing to and/or erasing the memory cell.
Therefore, the invention is based on the object of providing a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method which have improved charge retention properties.
In particular by virtue of the different configuration of the charge storage layer in the memory transistor and the selection transistor control layer in the selection transistor for the independent optimization of the associated threshold voltages, it is possible to realize an improvement in the charge retention properties in the memory transistor without impairing the electrical properties of the memory cell.
The selection transistor control layer (4*) and the charge storage layer (4) preferably have a different material or, in particular given the same semiconductor material, a different doping. In this way, a field reduction and thus an improvement in the charge retention can be effected in a targeted manner in the memory transistor, while the selection transistor has an essentially unchanged threshold voltage.
A semiconductor substrate with increased doping is preferably used, the selection transistor control layer and the charge storage layer having a semiconductor material with different doping. As a result, it is possible to reduce the electric fields in the memory transistor and thus a leakage current based on tunnelling (caused e.g. by imperfections (traps)), since this tunnelling current is exponentially dependent on the electric field. On the other hand, the resultant threshold voltage shift is compensated for by an adaptation of the work functions in the selection transistor control layer by means of an opposite doping, as a result of which the absolute threshold voltage of the selection transistor AT is reduced and the read current through the entire cell is thus increased. This in turn allows simpler evaluation circuits on the chip.
As an alternative to increasing the dopant concentration in the substrate, it is also possible only or additionally to dope the channel region or a surface of the substrate more heavily. Furthermore, as an alternative to the entire doping of the substrate or to the surface doping, it is also possible to use an increased well doping in order to modify the threshold voltage.
With regard to the method, a first insulation layer, an electrically conductive semiconductor layer, a second insulation layer and a further electrically conductive layer are formed, preferably both for the selection transistor and for the memory transistor, and patterned in such a way as to produce the two transistors with source and drain regions lying in between in the semiconductor substrate. In this case, an opposite doping is alternatively or additionally to be used only for the electrically conductive semiconductor layer of the selection transistor, in order to reduce the threshold voltage. In this way, a nonvolatile two-transistor semiconductor memory cell having improved charge retention properties can be fabricated in a particularly cost-effective manner.
The invention is described in more detail below using an exemplary embodiment with reference to the drawing.